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authorAlex Bennée2018-03-01 12:05:54 +0100
committerPeter Maydell2018-03-01 12:13:59 +0100
commit5eb70735af1c0b607bf2671a53aff3710cc1672f (patch)
tree4e49acfabfc565719f5470dc1141c25bd0187e8c /scripts
parentarm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 (diff)
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arm/helper.c: re-factor recpe and add recepe_f16
It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-23-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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