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| author | Alex Bennée | 2018-03-01 12:05:54 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-03-01 12:13:59 +0100 |
| commit | 5eb70735af1c0b607bf2671a53aff3710cc1672f (patch) | |
| tree | 4e49acfabfc565719f5470dc1141c25bd0187e8c /scripts | |
| parent | arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 (diff) | |
| download | qemu-5eb70735af1c0b607bf2671a53aff3710cc1672f.tar.gz qemu-5eb70735af1c0b607bf2671a53aff3710cc1672f.tar.xz qemu-5eb70735af1c0b607bf2671a53aff3710cc1672f.zip | |
arm/helper.c: re-factor recpe and add recepe_f16
It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions
