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| author | Alex Bennée | 2018-03-01 12:05:52 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-03-01 12:13:59 +0100 |
| commit | 6089030c7322d8f96b54fb9904e53b0f464bb8fe (patch) | |
| tree | c24eff10ae27383bf77b94fe9bca50c4f8b286d9 /scripts | |
| parent | arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed (diff) | |
| download | qemu-6089030c7322d8f96b54fb9904e53b0f464bb8fe.tar.gz qemu-6089030c7322d8f96b54fb9904e53b0f464bb8fe.tar.xz qemu-6089030c7322d8f96b54fb9904e53b0f464bb8fe.zip | |
arm/translate-a64: add FP16 x2 ops for simd_indexed
A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.
Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions