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| author | Maciej W. Rozycki | 2014-11-12 16:21:53 +0100 |
|---|---|---|
| committer | Leon Alrae | 2014-12-16 13:45:20 +0100 |
| commit | 7215d7e7aea85699bf516c3e8d84f6a22584da35 (patch) | |
| tree | aff3ab7544db394ba03ee41a4eb54f671d59a3db /scripts | |
| parent | target-mips: Correct the writes to Status and Cause registers via gdbstub (diff) | |
| download | qemu-7215d7e7aea85699bf516c3e8d84f6a22584da35.tar.gz qemu-7215d7e7aea85699bf516c3e8d84f6a22584da35.tar.xz qemu-7215d7e7aea85699bf516c3e8d84f6a22584da35.zip | |
target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP
Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by
using register addition operations.
This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R
and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands
to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying
`rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a
sign-extension from bit #31 is made, unless in the uninteresting case of
`rs' being 0, losing the upper 32 bits of the value copied for any
proper 64-bit values.
This also serves as an optimization as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions