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| author | Peter Maydell | 2017-07-11 12:21:26 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-07-11 12:21:26 +0200 |
| commit | 792dac309c8660306557ba058b8b5a6a75ab3c1f (patch) | |
| tree | c6448caf17db30d783454f82dfe09a99ba07baed /scripts | |
| parent | ARM: KVM: Enable in-kernel timers with user space gic (diff) | |
| download | qemu-792dac309c8660306557ba058b8b5a6a75ab3c1f.tar.gz qemu-792dac309c8660306557ba058b8b5a6a75ab3c1f.tar.xz qemu-792dac309c8660306557ba058b8b5a6a75ab3c1f.zip | |
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
For v7M, writes to the CONTROL register are only permitted for
privileged code. However even if the code is privileged, the
write must not affect the SPSEL bit in the CONTROL register
if the CPU is in Thread mode (as documented in the pseudocode
for the MSR instruction). Implement this, instead of permitting
SPSEL to be written in all cases.
This was causing mbed applications not to run, because the
RTX RTOS they use relies on this behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions