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| author | James Hogan | 2017-07-18 13:55:56 +0200 |
|---|---|---|
| committer | Yongbok Kim | 2017-07-20 23:42:26 +0200 |
| commit | cec56a733dd2c3fa81dbedbecf03922258747f7d (patch) | |
| tree | c8cac93783b4fd91c05c7ef2ef58b958961be694 /scripts | |
| parent | target/mips: Add an MMU mode for ERL (diff) | |
| download | qemu-cec56a733dd2c3fa81dbedbecf03922258747f7d.tar.gz qemu-cec56a733dd2c3fa81dbedbecf03922258747f7d.tar.xz qemu-cec56a733dd2c3fa81dbedbecf03922258747f7d.zip | |
target/mips: Add segmentation control registers
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
CP0_SegCtl2 control the behaviour and required privilege of the legacy
virtual memory segments.
Add them to the CP0 interface so they can be read and written when
CP0_Config3.SC=1, and initialise them to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions