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| author | Peter Maydell | 2018-10-24 08:50:18 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-24 08:51:36 +0200 |
| commit | eadb2febf05452bd8062c4c7823d7d789142500c (patch) | |
| tree | 5863f36441121ee9ce5130a0c94f675b9a194ac4 /scripts | |
| parent | target/arm: Implement HCR.VI and VF (diff) | |
| download | qemu-eadb2febf05452bd8062c4c7823d7d789142500c.tar.gz qemu-eadb2febf05452bd8062c4c7823d7d789142500c.tar.xz qemu-eadb2febf05452bd8062c4c7823d7d789142500c.zip | |
target/arm: Implement HCR.PTW
If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-8-peter.maydell@linaro.org
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions