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| author | Peter Maydell | 2019-05-10 13:03:57 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-06-13 16:14:03 +0200 |
| commit | fc1120a7f5f2d4b601003205c598077d3eb11ad2 (patch) | |
| tree | 4cbb5d4aea2f30badefb40b4ecb2ee16312bb433 /scripts | |
| parent | target/arm: Use tcg_gen_gvec_bitsel (diff) | |
| download | qemu-fc1120a7f5f2d4b601003205c598077d3eb11ad2.tar.gz qemu-fc1120a7f5f2d4b601003205c598077d3eb11ad2.tar.xz qemu-fc1120a7f5f2d4b601003205c598077d3eb11ad2.zip | |
target/arm: Implement NSACR gating of floating point
The NSACR register allows secure code to configure the FPU
to be inaccessible to non-secure code. If the NSACR.CP10
bit is set then:
* NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2)
* CPACR.{CP10,CP11} behave as if RAZ/WI
* HCPTR.{TCP11,TCP10} behave as if RAO/WI
Note that we do not implement the NSACR.NSASEDIS bit which
gates only access to Advanced SIMD, in the same way that
we don't implement the equivalent CPACR.ASEDIS and HCPTR.TASE.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190510110357.18825-1-peter.maydell@linaro.org
Diffstat (limited to 'scripts')
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