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authorEdgar E. Iglesias2021-03-08 23:46:36 +0100
committerPeter Maydell2021-03-12 13:40:09 +0100
commit9f61763574fb19525a68c46f3b8f763e5936a6fe (patch)
tree0465fcd543f6de9b77c45baf86cdb4184ee287be /stubs/arch_type.c
parentMerge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul... (diff)
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hw/misc: versal: Add a model of the XRAM controller
Add a model of the Xilinx Versal Accelerator RAM (XRAM). This is mainly a stub to make firmware happy. The size of the RAMs can be probed. The interrupt mask logic is modelled but none of the interrups will ever be raised unless injected. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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