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| author | Sergey Fedorov | 2015-10-16 12:14:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-10-16 14:13:48 +0200 |
| commit | 14cc7b54372995a6ba72c7719372e4f710fc9b5a (patch) | |
| tree | 2efd19b8eb1b3379450ec53ac711d62d2b6baeb4 /target-arm/cpu.h | |
| parent | misc: zynq_slcr: Fix MMIO writes (diff) | |
| download | qemu-14cc7b54372995a6ba72c7719372e4f710fc9b5a.tar.gz qemu-14cc7b54372995a6ba72c7719372e4f710fc9b5a.tar.xz qemu-14cc7b54372995a6ba72c7719372e4f710fc9b5a.zip | |
target-arm: Add MDCR_EL2
Add the MDCR_EL2 register. We don't implement any of
the debug-related traps this register controls yet, so
currently it simply reads back as written.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message; moved non-dummy definition from
debug_cp_reginfo to el2_cp_reginfo.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d1b5bc1a6f..e555122d17 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -380,6 +380,7 @@ typedef struct CPUARMState { uint64_t dbgwcr[16]; /* watchpoint control registers */ uint64_t mdscr_el1; uint64_t oslsr_el1; /* OS Lock Status */ + uint64_t mdcr_el2; /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ |