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| author | Peter Maydell | 2016-02-18 15:16:15 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-18 15:16:15 +0100 |
| commit | 187f678d5c28251dba2b44127e59966b14518ef7 (patch) | |
| tree | d4e18382adb7c6e12aab1f32bf6fd3def7821fab /target-arm/cpu.h | |
| parent | target-arm: Fix handling of SCR.SMD (diff) | |
| download | qemu-187f678d5c28251dba2b44127e59966b14518ef7.tar.gz qemu-187f678d5c28251dba2b44127e59966b14518ef7.tar.xz qemu-187f678d5c28251dba2b44127e59966b14518ef7.zip | |
target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps
Implement the traps to EL2 and EL3 controlled by the bits
MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap
accesses to the "powerdown debug" registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index afbf3661eb..77f9b51b76 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -595,6 +595,18 @@ void pmccntr_sync(CPUARMState *env); #define CPTR_TTA (1U << 20) #define CPTR_TFP (1U << 10) +#define MDCR_EPMAD (1U << 21) +#define MDCR_EDAD (1U << 20) +#define MDCR_SPME (1U << 17) +#define MDCR_SDD (1U << 16) +#define MDCR_TDRA (1U << 11) +#define MDCR_TDOSA (1U << 10) +#define MDCR_TDA (1U << 9) +#define MDCR_TDE (1U << 8) +#define MDCR_HPME (1U << 7) +#define MDCR_TPM (1U << 6) +#define MDCR_TPMCR (1U << 5) + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) |