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| author | Peter Maydell | 2016-10-24 17:26:56 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-10-24 17:26:56 +0200 |
| commit | 19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e (patch) | |
| tree | be8919d03be424ede566db09efe884a98fa13c30 /target-arm/cpu.h | |
| parent | hw/display: QOM'ify pl110.c (diff) | |
| download | qemu-19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e.tar.gz qemu-19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e.tar.xz qemu-19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e.zip | |
target-arm: Implement new HLT trap for semihosting
Version 2.0 of the semihosting specification introduces new trap
instructions for AArch32: HLT 0xF000 for A32 and HLT 0x3C for T32.
Implement these (in the same way we implement the existing HLT
semihosting trap for A64).
The old traps via SVC and BKPT are unaffected.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1476792973-18508-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6695390075..9d75227e04 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -52,7 +52,7 @@ #define EXCP_SMC 13 /* Secure Monitor Call */ #define EXCP_VIRQ 14 #define EXCP_VFIQ 15 -#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */ +#define EXCP_SEMIHOST 16 /* semihosting call */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 |