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| author | Peter Maydell | 2015-08-13 12:26:21 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-08-13 12:26:21 +0200 |
| commit | 49a661910c1374858602a3002b67115893673c25 (patch) | |
| tree | c837551eff756d10100f4bf869527ab7197b52f2 /target-arm/cpu.h | |
| parent | Introduce gic_class_name() instead of repeating condition (diff) | |
| download | qemu-49a661910c1374858602a3002b67115893673c25.tar.gz qemu-49a661910c1374858602a3002b67115893673c25.tar.xz qemu-49a661910c1374858602a3002b67115893673c25.zip | |
target-arm: Add debug check for mismatched cpreg resets
It's easy to accidentally define two cpregs which both try
to reset the same underlying state field (for instance a
clash between an AArch64 EL3 definition and an AArch32
banked register definition). if the two definitions disagree
about the reset value then the result is dependent on which
one happened to be reached last in the hashtable enumeration.
Add a consistency check to detect and assert in these cases:
after reset, we run a second pass where we check that the
reset operation doesn't change the value of the register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1436797559-20835-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7346c5f9d6..ebca342e42 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1448,6 +1448,9 @@ static inline bool cp_access_ok(int current_el, return (ri->access >> ((current_el * 2) + isread)) & 1; } +/* Raw read of a coprocessor register (as needed for migration, etc) */ +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); + /** * write_list_to_cpustate * @cpu: ARMCPU |