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| author | Peter Maydell | 2016-02-11 12:17:30 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-11 12:17:30 +0100 |
| commit | 5513c3abed8e5fabe116830c63f0d3fe1f94bd21 (patch) | |
| tree | 904144976ca6497e45e6cc11089b285e81652a47 /target-arm/cpu.h | |
| parent | target-arm: Fix typo in comment in arm_is_secure_below_el3() (diff) | |
| download | qemu-5513c3abed8e5fabe116830c63f0d3fe1f94bd21.tar.gz qemu-5513c3abed8e5fabe116830c63f0d3fe1f94bd21.tar.xz qemu-5513c3abed8e5fabe116830c63f0d3fe1f94bd21.zip | |
target-arm: Implement MDCR_EL3 and SDCR
Implement the MDCR_EL3 register (which is SDCR for AArch32).
For the moment we implement it as reads-as-written.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1454506721-11843-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 52284e9aaf..cf2df5032c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -382,6 +382,7 @@ typedef struct CPUARMState { uint64_t mdscr_el1; uint64_t oslsr_el1; /* OS Lock Status */ uint64_t mdcr_el2; + uint64_t mdcr_el3; /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ |