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| author | Edgar E. Iglesias | 2015-09-14 15:39:50 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-09-14 15:39:50 +0200 |
| commit | 68e9c2fe65bca7fc1bdc2411923333c3e87544a3 (patch) | |
| tree | 064471c06e5b575c8a3835394f3ff6f4205711d3 /target-arm/cpu.h | |
| parent | hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully (diff) | |
| download | qemu-68e9c2fe65bca7fc1bdc2411923333c3e87544a3.tar.gz qemu-68e9c2fe65bca7fc1bdc2411923333c3e87544a3.tar.xz qemu-68e9c2fe65bca7fc1bdc2411923333c3e87544a3.zip | |
target-arm: Add VTCR_EL2
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1442135278-25281-3-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed typo in comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index b9068c9dad..f91b7933b6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -224,6 +224,7 @@ typedef struct CPUARMState { }; /* MMU translation table base control. */ TCR tcr_el[4]; + TCR vtcr_el2; /* Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register |