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| author | Peter Maydell | 2016-06-17 16:23:45 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-06-17 16:23:51 +0200 |
| commit | 712058764da29b2908f6fbf56760ca4f15980709 (patch) | |
| tree | 8f3f9ff6f7df0b2db244f85a870dc2e2d6ecd288 /target-arm/cpu.h | |
| parent | bitops.h: Implement half-shuffle and half-unshuffle ops (diff) | |
| download | qemu-712058764da29b2908f6fbf56760ca4f15980709.tar.gz qemu-712058764da29b2908f6fbf56760ca4f15980709.tar.xz qemu-712058764da29b2908f6fbf56760ca4f15980709.zip | |
target-arm: Define new arm_is_el3_or_mon() function
The GICv3 system registers need to know if the CPU is AArch64
in EL3 or AArch32 in Monitor mode. This happens to be the first
part of the check for arm_is_secure(), so factor it out into a
new arm_is_el3_or_mon() function that the GIC can also use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 942aa36d9b..325b737d26 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1146,8 +1146,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) } } -/* Return true if the processor is in secure state */ -static inline bool arm_is_secure(CPUARMState *env) +/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ +static inline bool arm_is_el3_or_mon(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL3)) { if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { @@ -1159,6 +1159,15 @@ static inline bool arm_is_secure(CPUARMState *env) return true; } } + return false; +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ + if (arm_is_el3_or_mon(env)) { + return true; + } return arm_is_secure_below_el3(env); } |