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| author | Peter Maydell | 2016-02-19 15:39:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-26 16:09:42 +0100 |
| commit | a8d64e735182cbbb5dcc98f41656b118c45e57cc (patch) | |
| tree | 9edbf5a50ab9951f181571a41ba77ec70fc8baca /target-arm/cpu.h | |
| parent | target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 (diff) | |
| download | qemu-a8d64e735182cbbb5dcc98f41656b118c45e57cc.tar.gz qemu-a8d64e735182cbbb5dcc98f41656b118c45e57cc.tar.xz qemu-a8d64e735182cbbb5dcc98f41656b118c45e57cc.zip | |
target-arm: Fix handling of SDCR for 32-bit code
Fix two issues with our implementation of the SDCR:
* it is only present from ARMv8 onwards
* it does not contain several of the trap bits present in its 64-bit
counterpart the MDCR_EL3
Put the register description in the right place so that it does not
get enabled for ARMv7 and earlier, and give it a write function so that
we can mask out the bits which should not be allowed to have an effect
if EL3 is 32-bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1455892784-11328-2-git-send-email-peter.maydell@linaro.org
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 87720d4267..744f052a67 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -598,6 +598,7 @@ void pmccntr_sync(CPUARMState *env); #define MDCR_EDAD (1U << 20) #define MDCR_SPME (1U << 17) #define MDCR_SDD (1U << 16) +#define MDCR_SPD (3U << 14) #define MDCR_TDRA (1U << 11) #define MDCR_TDOSA (1U << 10) #define MDCR_TDA (1U << 9) @@ -606,6 +607,9 @@ void pmccntr_sync(CPUARMState *env); #define MDCR_TPM (1U << 6) #define MDCR_TPMCR (1U << 5) +/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ +#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) |