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author | Peter Maydell | 2014-04-15 20:18:43 +0200 |
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committer | Peter Maydell | 2014-04-17 22:34:04 +0200 |
commit | 2f2a00aec9838bc52ac4f5dd452f4cf533effa88 (patch) | |
tree | df3a0fae16a357f3ff1e17b17ca3d16c1bab5c3d /target-arm/internals.h | |
parent | target-arm: Implement AArch64 SPSR_EL1 (diff) | |
download | qemu-2f2a00aec9838bc52ac4f5dd452f4cf533effa88.tar.gz qemu-2f2a00aec9838bc52ac4f5dd452f4cf533effa88.tar.xz qemu-2f2a00aec9838bc52ac4f5dd452f4cf533effa88.zip |
target-arm: Move arm_log_exception() into internals.h
Move arm_log_exception() into internals.h so we can use it from
helper-a64.c for the AArch64 exception entry code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/internals.h')
-rw-r--r-- | target-arm/internals.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h index de79dfc316..d63a975a7e 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -39,6 +39,37 @@ static inline bool excp_is_internal(int excp) || excp == EXCP_STREX; } +/* Exception names for debug logging; note that not all of these + * precisely correspond to architectural exceptions. + */ +static const char * const excnames[] = { + [EXCP_UDEF] = "Undefined Instruction", + [EXCP_SWI] = "SVC", + [EXCP_PREFETCH_ABORT] = "Prefetch Abort", + [EXCP_DATA_ABORT] = "Data Abort", + [EXCP_IRQ] = "IRQ", + [EXCP_FIQ] = "FIQ", + [EXCP_BKPT] = "Breakpoint", + [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", + [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", + [EXCP_STREX] = "QEMU intercept of STREX", +}; + +static inline void arm_log_exception(int idx) +{ + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *exc = NULL; + + if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { + exc = excnames[idx]; + } + if (!exc) { + exc = "unknown"; + } + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + } +} + /* Scale factor for generic timers, ie number of ns per tick. * This gives a 62.5MHz timer. */ |