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| author | Peter Maydell | 2016-02-23 16:36:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-26 16:09:41 +0100 |
| commit | 50866ba5a2cfe922aaf3edb79f6eac5b0653477a (patch) | |
| tree | 39acd126ce238393135ebce39ea3ef42560ce58e /target-arm/op_helper.c | |
| parent | target-arm: Give CPSR setting on 32-bit exception return its own helper (diff) | |
| download | qemu-50866ba5a2cfe922aaf3edb79f6eac5b0653477a.tar.gz qemu-50866ba5a2cfe922aaf3edb79f6eac5b0653477a.tar.xz qemu-50866ba5a2cfe922aaf3edb79f6eac5b0653477a.zip | |
target-arm: Add write_type argument to cpsr_write()
Add an argument to cpsr_write() to indicate what kind of CPSR
write is being requested, since the exact behaviour should
differ for the different cases.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/op_helper.c')
| -rw-r--r-- | target-arm/op_helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index e3ddd5ad34..543d33aad2 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -422,13 +422,13 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { - cpsr_write(env, val, mask); + cpsr_write(env, val, mask, CPSRWriteByInstr); } /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { - cpsr_write(env, val, CPSR_ERET_MASK); + cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); } /* Access to user mode registers from privileged modes. */ @@ -780,7 +780,7 @@ void HELPER(exception_return)(CPUARMState *env) if (!return_to_aa64) { env->aarch64 = 0; env->uncached_cpsr = spsr & CPSR_M; - cpsr_write(env, spsr, ~0); + cpsr_write(env, spsr, ~0, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; } |