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| author | Sergey Fedorov | 2015-06-15 19:06:08 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-06-15 19:06:08 +0200 |
| commit | 13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932 (patch) | |
| tree | e73eef2e6b0e214024a2e0016f080f154cde0b2a /target-arm | |
| parent | hw/arm/virt: Add cortex-a53 cpu support in machine virt (diff) | |
| download | qemu-13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932.tar.gz qemu-13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932.tar.xz qemu-13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932.zip | |
target-arm: Fix REVIDR reset value
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1433321048-23793-2-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target-arm/cpu64.c | 2 | ||||
| -rw-r--r-- | target-arm/helper.c | 5 |
3 files changed, 5 insertions, 3 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ed5a6441bb..c80381da89 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -127,6 +127,7 @@ typedef struct ARMCPU { * prefix means a constant register. */ uint32_t midr; + uint32_t revidr; uint32_t reset_fpsid; uint32_t mvfr0; uint32_t mvfr1; diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index dd6f9d86f9..63c8b1cfa9 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; cpu->midr = 0x411fd070; + cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x12111111; @@ -161,6 +162,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->midr = 0x410fd034; + cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x12111111; diff --git a/target-arm/helper.c b/target-arm/helper.c index 611b0e7cdc..8053ad598b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3424,15 +3424,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; ARMCPRegInfo id_v8_midr_cp_reginfo[] = { /* v8 MIDR -- the wildcard isn't necessary, and nor is the - * variable-MIDR TI925 behaviour. Instead we have a single - * (strictly speaking IMPDEF) alias of the MIDR, REVIDR. + * variable-MIDR TI925 behaviour. */ { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] = { |