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| author | Edgar E. Iglesias | 2014-05-27 18:09:52 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-05-27 18:09:52 +0200 |
| commit | 2a923c4dde779fc3e5a55886bfa4085e590cbc96 (patch) | |
| tree | 89711b255a7ea964f4d0699f358ce7c5a0d09f94 /target-arm | |
| parent | target-arm: Add SPSR entries for EL2/HYP and EL3/MON (diff) | |
| download | qemu-2a923c4dde779fc3e5a55886bfa4085e590cbc96.tar.gz qemu-2a923c4dde779fc3e5a55886bfa4085e590cbc96.tar.xz qemu-2a923c4dde779fc3e5a55886bfa4085e590cbc96.zip | |
target-arm: A64: Introduce aarch64_banked_spsr_index()
Add aarch64_banked_spsr_index(), used to map an Exception Level
to an index in the banked_spsr array.
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-13-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper-a64.c | 2 | ||||
| -rw-r--r-- | target-arm/internals.h | 14 | ||||
| -rw-r--r-- | target-arm/op_helper.c | 3 |
3 files changed, 17 insertions, 2 deletions
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index b8e6d56b3b..b970fd1d69 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -488,7 +488,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[0] = pstate_read(env); + env->banked_spsr[aarch64_banked_spsr_index(1)] = pstate_read(env); env->sp_el[arm_current_pl(env)] = env->xregs[31]; env->xregs[31] = env->sp_el[1]; env->elr_el[1] = env->pc; diff --git a/target-arm/internals.h b/target-arm/internals.h index d63a975a7e..c9897c2cba 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -75,6 +75,20 @@ static inline void arm_log_exception(int idx) */ #define GTIMER_SCALE 16 +/* + * For AArch64, map a given EL to an index in the banked_spsr array. + */ +static inline unsigned int aarch64_banked_spsr_index(unsigned int el) +{ + static const unsigned int map[4] = { + [1] = 0, /* EL1. */ + [2] = 6, /* EL2. */ + [3] = 7, /* EL3. */ + }; + assert(el >= 1 && el <= 3); + return map[el]; +} + int bank_number(int mode); void switch_mode(CPUARMState *, int); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index f120b027b4..c2b4bf0fd7 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -386,7 +386,8 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) void HELPER(exception_return)(CPUARMState *env) { - uint32_t spsr = env->banked_spsr[0]; + unsigned int spsr_idx = aarch64_banked_spsr_index(1); + uint32_t spsr = env->banked_spsr[spsr_idx]; int new_el, i; if (env->pstate & PSTATE_SP) { |