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| author | Peter Maydell | 2015-06-15 19:06:11 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-06-15 19:06:11 +0200 |
| commit | 3977ee5d7a9f2e3664dd8b233f3224694e23b62b (patch) | |
| tree | 3ba600a3235d2c28eb62f1a7f46d4dd84964fa26 /target-arm | |
| parent | hw/arm/boot: fix rom_reset notifier registration order (diff) | |
| download | qemu-3977ee5d7a9f2e3664dd8b233f3224694e23b62b.tar.gz qemu-3977ee5d7a9f2e3664dd8b233f3224694e23b62b.tar.xz qemu-3977ee5d7a9f2e3664dd8b233f3224694e23b62b.zip | |
target-arm: Correct "preferred return address" for cpreg access exceptions
The architecture defines that when taking an exception trying to
access a coprocessor register, the "preferred return address" for
the exception is the address of the instruction that caused the
exception. Correct an off-by-4 error which meant we were returning
the address after the instruction for traps which happened because
of a failure of a runtime access-check function on an AArch32
register. (Traps caused by translate-time checkable permissions
failures had the correct address, as did traps on AArch64 registers.)
This fixes https://bugs.launchpad.net/qemu/+bug/1463338
Reported-by: Robert Buhren <robert@robertbuhren.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1433861440-30133-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 125b6da165..ead08f4820 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7175,7 +7175,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) break; } - gen_set_pc_im(s, s->pc); + gen_set_pc_im(s, s->pc - 4); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome); gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn); |