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| author | Peter Crosthwaite | 2014-04-15 20:49:11 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-04-17 22:34:06 +0200 |
| commit | db302f8f9364580a90b383d8531d28500e4e5bb5 (patch) | |
| tree | 34c9535b49f80c28e192d2973bfd51f29f6f3e19 /target-arm | |
| parent | allwinner-emac: update irq status after writes to interrupt registers (diff) | |
| download | qemu-db302f8f9364580a90b383d8531d28500e4e5bb5.tar.gz qemu-db302f8f9364580a90b383d8531d28500e4e5bb5.tar.xz qemu-db302f8f9364580a90b383d8531d28500e4e5bb5.zip | |
misc: zynq-slcr: Rewrite
Near total rewrite of this device model. It is stylistically
obsolete, has numerous coverity fails and is not up to date with latest
Xilinx documentation. Fix.
The registers are flattened into a single array. This greatly simplifies
the MMIO accessor functions.
We take the oppurtunity to update the register Macro definitions to
match the latest TRM. Xilinx has de-documented some regs hence there are
some straight deletions. We only do this however in the case or a stock
read-as-written reset-zero register. Non-zero resets are always
preserved. New register definitions are added as needed.
This all comes with a VMSD version break as the union layout from before
was a bit strange and we are better off without it.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 3aa016167b352ed224666909217137285fd3351d.1396503037.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
0 files changed, 0 insertions, 0 deletions