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authoredgar_igl2008-05-03 23:34:39 +0200
committeredgar_igl2008-05-03 23:34:39 +0200
commitaae6b32ae6253f7a6d7ebb1d77f9e34cc2e12553 (patch)
treee5dba6edd889ca4f081f0c3efe0b72130f7393c8 /target-cris/translate.c
parentSkip register moves when the target and the source are the same (diff)
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CRIS: Convert divide step to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4313 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/translate.c')
-rw-r--r--target-cris/translate.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 04632f57ec..76996b5ea4 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -375,6 +375,23 @@ static void t_gen_lz_i32(TCGv d, TCGv x)
tcg_gen_discard_i32(n);
}
+static void t_gen_cris_dstep(TCGv d, TCGv s)
+{
+ int l1;
+
+ l1 = gen_new_label();
+
+ /*
+ * d <<= 1
+ * if (d >= s)
+ * d -= s;
+ */
+ tcg_gen_shli_tl(d, d, 1);
+ tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
+ tcg_gen_sub_tl(d, d, s);
+ gen_set_label(l1);
+}
+
/* Extended arithmetics on CRIS. */
static inline void t_gen_add_flag(TCGv d, int flag)
{
@@ -725,7 +742,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
}
break;
case CC_OP_DSTEP:
- gen_op_dstep_T0_T1();
+ t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
break;
case CC_OP_BOUND:
{