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| author | Richard Henderson | 2015-08-29 21:59:29 +0200 |
|---|---|---|
| committer | Richard Henderson | 2015-10-07 11:36:27 +0200 |
| commit | 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 (patch) | |
| tree | 0d1aa7775d9cb83ce858394f2e56114ccdc23f94 /target-cris | |
| parent | tcg: Rename debug_insn_start to insn_start (diff) | |
| download | qemu-667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96.tar.gz qemu-667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96.tar.xz qemu-667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96.zip | |
target-*: Unconditionally emit tcg_gen_insn_start
While we're at it, emit the opcode adjacent to where we currently
record data for search_pc. This puts gen_io_start et al on the
"correct" side of the marker.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-cris')
| -rw-r--r-- | target-cris/translate.c | 5 | ||||
| -rw-r--r-- | target-cris/translate_v10.c | 3 |
2 files changed, 1 insertions, 7 deletions
diff --git a/target-cris/translate.c b/target-cris/translate.c index c5a22afa66..0a4b363dec 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -2994,10 +2994,6 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) int insn_len = 2; int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - /* Load a halfword onto the instruction register. */ dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); @@ -3197,6 +3193,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index 12d7dfc45e..3ab1c398e0 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1199,9 +1199,6 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc) { unsigned int insn_len = 2; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_insn_start(dc->pc); - /* Load a halfword onto the instruction register. */ dc->ir = cpu_lduw_code(env, dc->pc); |