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authorAndre Przywara2009-08-19 15:42:41 +0200
committerAnthony Liguori2009-08-28 02:33:15 +0200
commitac72472b5fb8411fbeb6789187d67ad7aef69133 (patch)
tree1d9b5bba216b685ce3327526d9f16b8fa7d66662 /target-i386/helper.c
parentextend -smp parsing to include cores= and threads= options (diff)
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push CPUID level to 4 to allow Intel multicore decoding
Intel CPUs store the number of cores in CPUID leaf 4. So push the maxleaf value to 4 to allow the guests access to this leaf. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-i386/helper.c')
-rw-r--r--target-i386/helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c
index e18a5a9c53..afdd3e4dcf 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -119,7 +119,7 @@ static x86_def_t x86_defs[] = {
#ifdef TARGET_X86_64
{
.name = "qemu64",
- .level = 2,
+ .level = 4,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
.vendor3 = CPUID_VENDOR_AMD_3,
@@ -190,7 +190,7 @@ static x86_def_t x86_defs[] = {
#endif
{
.name = "qemu32",
- .level = 2,
+ .level = 4,
.family = 6,
.model = 3,
.stepping = 3,