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authorFernando Luis Vázquez Cao2013-12-06 09:38:24 +0100
committerPaolo Bonzini2013-12-12 13:12:42 +0100
commitf86746c263753cf7a7e4bdb8829c70272dfcf36c (patch)
tree9f04a3e2820e391102aca5f57e75f00571412da9 /target-i386/kvm.c
parenttarget-i386: Intel MPX (diff)
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target-i386: do not special case TSC writeback
Newer kernels are capable of synchronizing TSC values of multiple VCPUs on writeback, but we were excluding the power up case, which is not needed anymore. Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Fernando Luis Vázquez Cao <fernando_b1@lab.ntt.co.jp>
Diffstat (limited to 'target-i386/kvm.c')
-rw-r--r--target-i386/kvm.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 01ebca24f0..312a46bcb9 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1151,15 +1151,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
#endif
if (level == KVM_PUT_FULL_STATE) {
- /*
- * KVM is yet unable to synchronize TSC values of multiple VCPUs on
- * writeback. Until this is fixed, we only write the offset to SMP
- * guests after migration, desynchronizing the VCPUs, but avoiding
- * huge jump-backs that would occur without any writeback at all.
- */
- if (smp_cpus == 1 || env->tsc != 0) {
- kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
- }
+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
}
/*
* The following MSRs have side effects on the guest or are too heavy