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| author | Aurelien Jarno | 2010-07-01 23:43:34 +0200 |
|---|---|---|
| committer | Aurelien Jarno | 2010-07-01 23:45:28 +0200 |
| commit | afa88c3ae5fb6b2dce4e6221b4cf2664b05adcc5 (patch) | |
| tree | a191ba5c025fde087f19117c09a421ddc1b9a544 /target-i386/translate.c | |
| parent | target-mips: split load and store (diff) | |
| download | qemu-afa88c3ae5fb6b2dce4e6221b4cf2664b05adcc5.tar.gz qemu-afa88c3ae5fb6b2dce4e6221b4cf2664b05adcc5.tar.xz qemu-afa88c3ae5fb6b2dce4e6221b4cf2664b05adcc5.zip | |
target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386/translate.c')
0 files changed, 0 insertions, 0 deletions