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| author | Peter Maydell | 2014-09-12 16:12:26 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-09-12 16:12:26 +0200 |
| commit | 4c24f4004089a308c5de8ed720cf6bd1746aedd8 (patch) | |
| tree | d83f318edd5b987a94d0a16ed8a25a215c645fca /target-lm32/helper.c | |
| parent | libqos virtio: Increase ISR timeout (diff) | |
| parent | hw/arm/boot: enable DTB support when booting ELF images (diff) | |
| download | qemu-4c24f4004089a308c5de8ed720cf6bd1746aedd8.tar.gz qemu-4c24f4004089a308c5de8ed720cf6bd1746aedd8.tar.xz qemu-4c24f4004089a308c5de8ed720cf6bd1746aedd8.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140912' into staging
target-arm:
* add "linux,stdout-path" to the virt DTB
* fix a long standing bug with IRQ disabling on Cortex-M CPUs
* implement input interrupt logic in the PL061
* fix failure to load correct SP/PC on reset of Cortex-M CPUs
if the vector table is not in a ROM-blob-in-RAM
* provide flash devices for boot ROMs in the virt board
* implement architectural watchpoints
* fix misimplementation of Inner Shareable TLB operations that
caused instability of guests in TCG SMP configurations
* configure PL011 and PL031 in the virt board correctly with
level-triggered interrupts rather than edge-triggered
* support providing a device tree blob to ROM (firmware)
images as well as to kernels
# gpg: Signature made Fri 12 Sep 2014 14:19:08 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20140912: (23 commits)
hw/arm/boot: enable DTB support when booting ELF images
hw/arm/boot: load device tree to base of DRAM if no -kernel option was passed
hw/arm/boot: pass an address limit to and return size from load_dtb()
hw/arm/boot: load DTB as a ROM image
hw/arm/virt: fix pl011 and pl031 irq flags
target-arm: Make *IS TLB maintenance ops affect all CPUs
target-arm: Push legacy wildcard TLB ops back into v6
target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0
target-arm: Remove comment about MDSCR_EL1 being dummy implementation
target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32
target-arm: Implement handling of fired watchpoints
target-arm: Move extended_addresses_enabled() to internals.h
target-arm: Implement setting of watchpoints
cpu-exec: Make debug_excp_handler a QOM CPU method
exec.c: Record watchpoint fault address and direction
exec.c: Provide full set of dummy wp remove functions in user-mode
exec.c: Relax restrictions on watchpoint length and alignment
hw/arm/virt: Provide flash devices for boot ROMs
target-arm: Fix broken indentation in arm_cpu_reest()
target-arm: Fix resetting issues on ARMv7-M CPUs
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-lm32/helper.c')
| -rw-r--r-- | target-lm32/helper.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 1bca1961af..ad724aecbc 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -125,9 +125,10 @@ static bool check_watchpoints(CPULM32State *env) return false; } -void lm32_debug_excp_handler(CPULM32State *env) +void lm32_debug_excp_handler(CPUState *cs) { - CPUState *cs = CPU(lm32_env_get_cpu(env)); + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; CPUBreakpoint *bp; if (cs->watchpoint_hit) { |