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| author | aurel32 | 2008-11-11 12:39:33 +0100 |
|---|---|---|
| committer | aurel32 | 2008-11-11 12:39:33 +0100 |
| commit | 2623c1ecfc87a0a86188c75598410e6b3d0f18a3 (patch) | |
| tree | 84e8343c15a8915ff03dc0bab22f6d9a0a5c2e59 /target-mips/cpu.h | |
| parent | target-mips: optimize gen_op_addr_add() (1/2) (diff) | |
| download | qemu-2623c1ecfc87a0a86188c75598410e6b3d0f18a3.tar.gz qemu-2623c1ecfc87a0a86188c75598410e6b3d0f18a3.tar.xz qemu-2623c1ecfc87a0a86188c75598410e6b3d0f18a3.zip | |
target-mips: optimize gen_op_addr_add() (2/2)
Instead of dynamically generating different code depending on the UX
flag, add a new flag in ctx->flags to generate different code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5677 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index a27ffd3bd0..d686f8e255 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -411,7 +411,7 @@ struct CPUMIPSState { int error_code; uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x01FF +#define MIPS_HFLAG_TMASK 0x03FF #define MIPS_HFLAG_MODE 0x0007 /* execution modes */ /* The KSU flags must be the lowest bits in hflags. The flag order must be the same as defined for CP0 Status. This allows to use @@ -430,15 +430,16 @@ struct CPUMIPSState { and RSQRT.D. */ #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ +#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ /* If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce * this from three bits to two. */ -#define MIPS_HFLAG_BMASK 0x0e00 -#define MIPS_HFLAG_B 0x0200 /* Unconditional branch */ -#define MIPS_HFLAG_BC 0x0400 /* Conditional branch */ -#define MIPS_HFLAG_BL 0x0600 /* Likely branch */ -#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */ +#define MIPS_HFLAG_BMASK 0x1C00 +#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ +#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ +#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ +#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ target_ulong btarget; /* Jump / branch target */ int bcond; /* Branch condition (if needed) */ |