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| author | ths | 2007-12-25 04:13:56 +0100 |
|---|---|---|
| committer | ths | 2007-12-25 04:13:56 +0100 |
| commit | 6d35524c40a7c884462b852ae697f16f7c90ee9e (patch) | |
| tree | abed8cba63ecd2c560705afbb1c65579eb86d0d4 /target-mips/cpu.h | |
| parent | One more bit of alpha support. (diff) | |
| download | qemu-6d35524c40a7c884462b852ae697f16f7c90ee9e.tar.gz qemu-6d35524c40a7c884462b852ae697f16f7c90ee9e.tar.xz qemu-6d35524c40a7c884462b852ae697f16f7c90ee9e.zip | |
Improved PABITS handling, and config register fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3855 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 482f27d1e2..a08a634bcb 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -162,6 +162,8 @@ struct CPUMIPSState { uint32_t SEGBITS; target_ulong SEGMask; + uint32_t PABITS; + target_ulong PAMask; int32_t CP0_Index; /* CP0_MVP* are per MVP registers. */ |