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| author | ths | 2008-05-06 12:57:59 +0200 |
|---|---|---|
| committer | ths | 2008-05-06 12:57:59 +0200 |
| commit | 958fb4a92cbbb2b9b49e4b4502a836c71435570a (patch) | |
| tree | dc0e1f00ef92b9017ab0ad60e80ba1816766ad56 /target-mips/cpu.h | |
| parent | Fix MIPS64 branches. Funny how this survived testing. (diff) | |
| download | qemu-958fb4a92cbbb2b9b49e4b4502a836c71435570a.tar.gz qemu-958fb4a92cbbb2b9b49e4b4502a836c71435570a.tar.xz qemu-958fb4a92cbbb2b9b49e4b4502a836c71435570a.zip | |
Use TCG for MIPS GPR moves.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4356 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 957b6e8d66..49b7e63a49 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -158,6 +158,7 @@ struct CPUMIPSState { CPUMIPSTLBContext *tlb; CPUMIPSFPUContext *fpu; uint32_t current_tc; + target_ulong *current_tc_gprs; uint32_t SEGBITS; target_ulong SEGMask; |