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| author | ths | 2007-03-18 13:43:40 +0100 |
|---|---|---|
| committer | ths | 2007-03-18 13:43:40 +0100 |
| commit | 39d51eb8bcc603c02342d8f5e1f7a569e5f17e06 (patch) | |
| tree | 3036073718e3ba76bc3143261d6caee489d03538 /target-mips/helper.c | |
| parent | As icbi is not a priviledge instruction and is treated as a load by the MMU (diff) | |
| download | qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.tar.gz qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.tar.xz qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.zip | |
Fix BD flag handling, cause register contents, implement some more bits
for R2 interrupt handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 9ba401785b..0b23f359f0 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -295,9 +295,12 @@ void do_interrupt (CPUState *env) /* If the exception was raised from a delay slot, come back to the jump. */ env->CP0_DEPC = env->PC - 4; + if (!(env->hflags & MIPS_HFLAG_EXL)) + env->CP0_Cause |= (1 << CP0Ca_BD); env->hflags &= ~MIPS_HFLAG_BMASK; } else { env->CP0_DEPC = env->PC; + env->CP0_Cause &= ~(1 << CP0Ca_BD); } enter_debug_mode: env->hflags |= MIPS_HFLAG_DM; @@ -318,9 +321,12 @@ void do_interrupt (CPUState *env) /* If the exception was raised from a delay slot, come back to the jump. */ env->CP0_ErrorEPC = env->PC - 4; + if (!(env->hflags & MIPS_HFLAG_EXL)) + env->CP0_Cause |= (1 << CP0Ca_BD); env->hflags &= ~MIPS_HFLAG_BMASK; } else { env->CP0_ErrorEPC = env->PC; + env->CP0_Cause &= ~(1 << CP0Ca_BD); } env->hflags |= MIPS_HFLAG_ERL; env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); @@ -364,7 +370,8 @@ void do_interrupt (CPUState *env) goto set_EPC; case EXCP_CpU: cause = 11; - env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28); + env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | + (env->error_code << CP0Ca_CE); goto set_EPC; case EXCP_OVERFLOW: cause = 12; @@ -385,11 +392,12 @@ void do_interrupt (CPUState *env) /* If the exception was raised from a delay slot, come back to the jump. */ env->CP0_EPC = env->PC - 4; - env->CP0_Cause |= 0x80000000; + if (!(env->hflags & MIPS_HFLAG_EXL)) + env->CP0_Cause |= (1 << CP0Ca_BD); env->hflags &= ~MIPS_HFLAG_BMASK; } else { env->CP0_EPC = env->PC; - env->CP0_Cause &= ~0x80000000; + env->CP0_Cause &= ~(1 << CP0Ca_BD); } if (env->CP0_Status & (1 << CP0St_BEV)) { env->PC = (int32_t)0xBFC00200; |