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| author | Leon Alrae | 2015-03-20 13:06:10 +0100 |
|---|---|---|
| committer | Leon Alrae | 2015-06-12 10:04:51 +0200 |
| commit | b435f3f3d174721382b55bbd0c785ec50c1796a9 (patch) | |
| tree | bd60a78cb9d00642e688bff99f31ed5f3c75f719 /target-mips/translate.c | |
| parent | net/dp8393x: fix hardware reset (diff) | |
| download | qemu-b435f3f3d174721382b55bbd0c785ec50c1796a9.tar.gz qemu-b435f3f3d174721382b55bbd0c785ec50c1796a9.tar.xz qemu-b435f3f3d174721382b55bbd0c785ec50c1796a9.zip | |
target-mips: correct MFC0 for CP0.EntryLo in MIPS64
CP0.EntryLo bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index f6ae0d3aec..2cc58756f2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4964,10 +4964,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif @@ -5019,10 +5019,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif |