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| author | Maciej W. Rozycki | 2014-12-21 00:00:25 +0100 |
|---|---|---|
| committer | Leon Alrae | 2015-02-13 15:09:28 +0100 |
| commit | 196a7958c65778d05a491309377a65c58f643a1c (patch) | |
| tree | 769360f034aedcbc253f1a2f1b84dd4714d99306 /target-mips | |
| parent | isa: remove isa_mem_base variable (diff) | |
| download | qemu-196a7958c65778d05a491309377a65c58f643a1c.tar.gz qemu-196a7958c65778d05a491309377a65c58f643a1c.tar.xz qemu-196a7958c65778d05a491309377a65c58f643a1c.zip | |
target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 1543f6c388..9e8433a919 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -474,7 +474,7 @@ static const mips_def_t mips_defs[] = .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, + .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, .insn_flags = CPU_MIPS64, @@ -575,7 +575,7 @@ static const mips_def_t mips_defs[] = .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, + .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, .insn_flags = CPU_MIPS64R2, |