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| author | 陳韋任 (Wei-Ren Chen) | 2012-11-14 03:49:55 +0100 |
|---|---|---|
| committer | Aurelien Jarno | 2012-11-15 14:48:16 +0100 |
| commit | 6801038bc52d61f81ac8a25fbe392f1bad982887 (patch) | |
| tree | eb11fc0be31e6f07b8dce5e8ce3994fd818e954d /target-mips | |
| parent | mips/malta: fix CBUS UART interrupt pin (diff) | |
| download | qemu-6801038bc52d61f81ac8a25fbe392f1bad982887.tar.gz qemu-6801038bc52d61f81ac8a25fbe392f1bad982887.tar.xz qemu-6801038bc52d61f81ac8a25fbe392f1bad982887.zip | |
target-mips: fix wrong microMIPS opcode encoding
While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.
[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
Application-Specific Extension to the microMIPS32 Architecture
Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index f6fc0c27ae..01b48fa2a2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -10385,7 +10385,7 @@ enum { /* bits 13..12 for 0x32 */ MULT_ACC = 0x0, - MULTU_ACC = 0x0, + MULTU_ACC = 0x1, /* bits 15..12 for 0x2c */ SEB = 0x2, |