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| author | Yongbok Kim | 2015-06-30 17:33:15 +0200 |
|---|---|---|
| committer | Leon Alrae | 2015-07-15 15:07:20 +0200 |
| commit | 6b9c26fb5eed2345398daca4eef601da2f3d7867 (patch) | |
| tree | 285285860c7d2e441592aea59bc9f777d9b514b4 /target-mips | |
| parent | target-mips: fix to clear MSACSR.Cause (diff) | |
| download | qemu-6b9c26fb5eed2345398daca4eef601da2f3d7867.tar.gz qemu-6b9c26fb5eed2345398daca4eef601da2f3d7867.tar.xz qemu-6b9c26fb5eed2345398daca4eef601da2f3d7867.zip | |
disas/mips: fix disassembling R6 instructions
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
and CACHE instructions have 9 bits offsets.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
0 files changed, 0 insertions, 0 deletions