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| author | Maciej W. Rozycki | 2014-11-03 19:47:45 +0100 |
|---|---|---|
| committer | Leon Alrae | 2014-12-16 13:45:19 +0100 |
| commit | 800675f11742b6080e40d17b8d5f35d3a5fc5724 (patch) | |
| tree | 4c045b49cd4895afa41cecfc2ff3304fc1096f1e /target-mips | |
| parent | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (diff) | |
| download | qemu-800675f11742b6080e40d17b8d5f35d3a5fc5724.tar.gz qemu-800675f11742b6080e40d17b8d5f35d3a5fc5724.tar.xz qemu-800675f11742b6080e40d17b8d5f35d3a5fc5724.zip | |
target-mips: Correct the handling of register #72 on writes
Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it. This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/gdbstub.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c index f65fec23cc..7e3a604afa 100644 --- a/target-mips/gdbstub.c +++ b/target-mips/gdbstub.c @@ -90,7 +90,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return sizeof(target_ulong); } if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >= 38 && n < 73) { + && n >= 38 && n < 72) { if (n < 70) { if (env->CP0_Status & (1 << CP0St_FR)) { env->active_fpu.fpr[n - 38].d = tmp; |