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author | Andreas Färber | 2013-08-26 03:01:33 +0200 |
---|---|---|
committer | Andreas Färber | 2014-03-13 19:20:46 +0100 |
commit | 7510454e3e74aafa2e6c50388bf24904644b6a96 (patch) | |
tree | d529c51ffa5633e8e067ae092bbc33bcf9a7bd8f /target-openrisc | |
parent | target-m68k: Remove custom qemu_assert() function (diff) | |
download | qemu-7510454e3e74aafa2e6c50388bf24904644b6a96.tar.gz qemu-7510454e3e74aafa2e6c50388bf24904644b6a96.tar.xz qemu-7510454e3e74aafa2e6c50388bf24904644b6a96.zip |
cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
Note that while such functions may exist both for *-user and softmmu,
only *-user uses the CPUState hook, while softmmu reuses the prototype
for calling it directly.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc')
-rw-r--r-- | target-openrisc/cpu.c | 4 | ||||
-rw-r--r-- | target-openrisc/cpu.h | 4 | ||||
-rw-r--r-- | target-openrisc/mmu.c | 14 | ||||
-rw-r--r-- | target-openrisc/mmu_helper.c | 3 |
4 files changed, 13 insertions, 12 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 0b2ffb23f0..99e4aa7c67 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -165,7 +165,9 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; cc->gdb_write_register = openrisc_cpu_gdb_write_register; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; +#else cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index ae9d17f102..660bb4f1e7 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -353,15 +353,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, - target_ulong address, +int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_list cpu_openrisc_list #define cpu_exec cpu_openrisc_exec #define cpu_gen_code cpu_openrisc_gen_code -#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault #define cpu_signal_handler cpu_openrisc_signal_handler #ifndef CONFIG_USER_ONLY diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index dd487bd0d1..1fd0a0a3fa 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -174,19 +174,19 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, } #ifndef CONFIG_USER_ONLY -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, - target_ulong address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, + vaddr address, int rw, int mmu_idx) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); int ret = 0; hwaddr physical = 0; int prot = 0; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, address, rw); if (ret == TLBRET_MATCH) { - tlb_set_page(env, address & TARGET_PAGE_MASK, + tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); ret = 0; @@ -198,11 +198,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, return ret; } #else -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, - target_ulong address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, + vaddr address, int rw, int mmu_idx) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); int ret = 0; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); ret = 1; diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c index e46b092984..b023a5fb98 100644 --- a/target-openrisc/mmu_helper.c +++ b/target-openrisc/mmu_helper.c @@ -39,9 +39,10 @@ void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { + OpenRISCCPU *cpu = openrisc_env_get_cpu(env); int ret; - ret = cpu_openrisc_handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); if (ret) { if (retaddr) { |