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| author | David Gibson | 2013-03-12 01:31:47 +0100 |
|---|---|---|
| committer | Alexander Graf | 2013-03-22 15:28:53 +0100 |
| commit | f80872e21c07edd06eb343eeeefc8af404b518a6 (patch) | |
| tree | 9334b1d60ca24bfed9d73b0f4b8f072cb20ec25e /target-ppc/cpu.h | |
| parent | mmu-hash*: Merge translate and fault handling functions (diff) | |
| download | qemu-f80872e21c07edd06eb343eeeefc8af404b518a6.tar.gz qemu-f80872e21c07edd06eb343eeeefc8af404b518a6.tar.xz qemu-f80872e21c07edd06eb343eeeefc8af404b518a6.zip | |
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional page
protection mechanism. Each virtual page has a "class" (0-31) recorded in
the PTE. The AMR register contains bits which can prohibit reads and/or
writes on a class by class basis. Interestingly, the AMR is userspace
readable and writable, however user mode writes are masked by the contents
of the UAMOR which is privileged.
This patch implements this protection mechanism, along with the AMR and
UAMOR SPRs. The architecture also specifies a hypervisor-privileged AMOR
register which masks user and supervisor writes to the AMR and UAMOR. We
leave this out for now, since we don't at present model hypervisor mode
correctly in any case.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
[agraf: fix 32-bit hosts]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index e96afa61ec..eb793e03c0 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -113,11 +113,13 @@ enum powerpc_mmu_t { #if defined(TARGET_PPC64) #define POWERPC_MMU_64 0x00010000 #define POWERPC_MMU_1TSEG 0x00020000 +#define POWERPC_MMU_AMR 0x00040000 /* 64 bits PowerPC MMU */ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments) */ + POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG + | POWERPC_MMU_AMR | 0x00000003, + /* Architecture 2.06 "degraded" (no 1T segments or AMR) */ POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003, #endif /* defined(TARGET_PPC64) */ }; @@ -1223,6 +1225,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_601_UDECR (0x006) #define SPR_LR (0x008) #define SPR_CTR (0x009) +#define SPR_UAMR (0x00C) #define SPR_DSCR (0x011) #define SPR_DSISR (0x012) #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ @@ -1260,6 +1263,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_MPC_CMPH (0x09B) #define SPR_MPC_LCTRL1 (0x09C) #define SPR_MPC_LCTRL2 (0x09D) +#define SPR_UAMOR (0x09D) #define SPR_MPC_ICTRL (0x09E) #define SPR_MPC_BAR (0x09F) #define SPR_VRSAVE (0x100) |