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authorBenjamin Herrenschmidt2016-07-27 08:56:41 +0200
committerDavid Gibson2016-09-07 04:40:10 +0200
commit3433b732a4c9abb413eb39a6badb63e83ad2288c (patch)
tree82a1c93d253ce3f35acd9de6892e66d2839ffdce /target-ppc/excp_helper.c
parentppc: Don't update NIP in dcbz and lscbx (diff)
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ppc: Make alignment exceptions suck less
The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/excp_helper.c')
-rw-r--r--target-ppc/excp_helper.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 882d529dbe..04ed4da1f4 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -260,11 +260,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* XXX: this is false */
/* Get rS/rD and rA from faulting opcode */
- /* Broken for LE mode */
- env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip)
- & 0x03FF0000) >> 16;
+ /* Note: the opcode fields will not be set properly for a direct
+ * store load/store, but nobody cares as nobody actually uses
+ * direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {