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authorNicholas Piggin2016-10-20 08:59:10 +0200
committerDavid Gibson2016-10-28 00:36:58 +0200
commitf85bcec31ee578eccf6182be158d6ac6d9b90a4c (patch)
tree567e904942415e82c526d49bb4cfffbb30d86cba /target-ppc/excp_helper.c
parentppc/xics: change the icp_ routines API to use an 'ICPState *' argument (diff)
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ppc: fix MSR_ME handling for system reset interrupt
Power ISA specifies ME bit handling for system reset interrupt: if the interrupt occurred while the thread was in power-saving mode, set to 1; otherwise not altered Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/excp_helper.c')
-rw-r--r--target-ppc/excp_helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 921c39d33f..53c407576b 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
srr1 = SPR_BOOKE_CSRR1;
break;
case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
/* indicate that we resumed from power save mode */
msr |= 0x10000;
- } else {
- new_msr &= ~((target_ulong)1 << MSR_ME);
+ new_msr |= ((target_ulong)1 << MSR_ME);
}
new_msr |= (target_ulong)MSR_HVB;