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| author | Alexander Graf | 2011-04-30 23:34:58 +0200 |
|---|---|---|
| committer | Alexander Graf | 2011-05-12 00:24:51 +0200 |
| commit | 01662f3e513399107c7278f2ee8f6ee4cf03fa70 (patch) | |
| tree | b46451002c0cbfb049afc83acfd416f18b81a709 /target-ppc/helper.h | |
| parent | PPC: Add another 64 bits to instruction feature mask (diff) | |
| download | qemu-01662f3e513399107c7278f2ee8f6ee4cf03fa70.tar.gz qemu-01662f3e513399107c7278f2ee8f6ee4cf03fa70.tar.xz qemu-01662f3e513399107c7278f2ee8f6ee4cf03fa70.zip | |
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.
This patch adds support for the FSL style MMU.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/helper.h')
| -rw-r--r-- | target-ppc/helper.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 7c02be9cfd..51c99c816f 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -334,6 +334,12 @@ DEF_HELPER_1(4xx_tlbsx, tl, tl) DEF_HELPER_2(440_tlbre, tl, i32, tl) DEF_HELPER_3(440_tlbwe, void, i32, tl, tl) DEF_HELPER_1(440_tlbsx, tl, tl) +DEF_HELPER_0(booke206_tlbre, void) +DEF_HELPER_0(booke206_tlbwe, void) +DEF_HELPER_1(booke206_tlbsx, void, tl) +DEF_HELPER_1(booke206_tlbivax, void, tl) +DEF_HELPER_1(booke206_tlbflush, void, i32) +DEF_HELPER_2(booke_setpid, void, i32, tl) DEF_HELPER_1(6xx_tlbd, void, tl) DEF_HELPER_1(6xx_tlbi, void, tl) DEF_HELPER_1(74xx_tlbd, void, tl) |