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author | Andreas Färber | 2013-09-03 13:59:37 +0200 |
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committer | Andreas Färber | 2014-03-13 19:52:47 +0100 |
commit | 0c591eb0a9d0593d71d7cb61f4184222ac14fdd2 (patch) | |
tree | 27fc876065b6ed65266b3615a424e6e2cafdfd30 /target-ppc/mmu-hash64.c | |
parent | cputlb: Change tlb_flush() argument to CPUState (diff) | |
download | qemu-0c591eb0a9d0593d71d7cb61f4184222ac14fdd2.tar.gz qemu-0c591eb0a9d0593d71d7cb61f4184222ac14fdd2.tar.xz qemu-0c591eb0a9d0593d71d7cb61f4184222ac14fdd2.zip |
cputlb: Change tlb_set_page() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-ppc/mmu-hash64.c')
-rw-r--r-- | target-ppc/mmu-hash64.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 3f405b3cc9..1fefe5881e 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -476,7 +476,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, /* Translation is off */ /* In real mode the top 4 effective address bits are ignored */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); return 0; @@ -578,7 +578,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, raddr = ppc_hash64_pte_raddr(slb, pte, eaddr); - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return 0; |