diff options
| author | Nikunj A Dadhania | 2016-09-20 18:34:59 +0200 |
|---|---|---|
| committer | David Gibson | 2016-09-23 04:39:06 +0200 |
| commit | a8a6d53e3626e96d5a37b9eb6dc6ce759714502e (patch) | |
| tree | a27e029768b808905c727a1907682d03eb829c6d /target-ppc/mmu_helper.c | |
| parent | spapr: Introduce sPAPRCPUCoreClass (diff) | |
| download | qemu-a8a6d53e3626e96d5a37b9eb6dc6ce759714502e.tar.gz qemu-a8a6d53e3626e96d5a37b9eb6dc6ce759714502e.tar.xz qemu-a8a6d53e3626e96d5a37b9eb6dc6ce759714502e.zip | |
target-ppc: add TLB_NEED_LOCAL_FLUSH flag
Introduces bit-flag in CPUPPCState::tlb_need_flush:
TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb
This would indicate a pending local tlb flush (isync instructions,
interrupts, ...)
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/mmu_helper.c')
| -rw-r--r-- | target-ppc/mmu_helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 696bb03ab5..d59d2f83d2 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1965,7 +1965,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) * we just mark the TLB to be flushed later (context synchronizing * event or sync instruction on 32-bit). */ - env->tlb_need_flush = 1; + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: @@ -1979,7 +1979,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * we just invalidate all TLBs */ - env->tlb_need_flush = 1; + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; break; #endif /* defined(TARGET_PPC64) */ default: @@ -2065,7 +2065,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) } } #else - env->tlb_need_flush = 1; + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; #endif } } |