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| author | Alexander Graf | 2014-01-19 17:50:09 +0100 |
|---|---|---|
| committer | Alexander Graf | 2014-06-16 13:24:35 +0200 |
| commit | 4d09d5291dac27b48fd597c72de6fddaa4d74571 (patch) | |
| tree | b7c4afad4ff6711de9edb8025a5f188e4fffb20c /target-ppc | |
| parent | PPC: Properly emulate L1CSR0 and L1CSR1 (diff) | |
| download | qemu-4d09d5291dac27b48fd597c72de6fddaa4d74571.tar.gz qemu-4d09d5291dac27b48fd597c72de6fddaa4d74571.tar.xz qemu-4d09d5291dac27b48fd597c72de6fddaa4d74571.zip | |
PPC: Add dcbtls emulation
The dcbtls instruction is able to lock data inside the L1 cache.
Unfortunately we don't emulate any caches, so we have to tell the guest
that its locking attempt failed.
However, by implementing the instruction we at least don't give the
guest a program exception which it definitely does not expect.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 7be776f161..a2402835eb 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4481,6 +4481,17 @@ static void gen_dcbtst(DisasContext *ctx) */ } +/* dcbtls */ +static void gen_dcbtls(DisasContext *ctx) +{ + /* Always fails locking the cache */ + TCGv t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_Exxx_L1CSR0); + tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); + gen_store_spr(SPR_Exxx_L1CSR0, t0); + tcg_temp_free(t0); +} + /* dcbz */ static void gen_dcbz(DisasContext *ctx) { @@ -10215,6 +10226,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), +GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), |