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| author | Aurelien Jarno | 2015-05-25 01:28:56 +0200 |
|---|---|---|
| committer | Aurelien Jarno | 2015-06-12 12:02:48 +0200 |
| commit | a2368e01c95a093d250a0e5d3cef53dddf642f1e (patch) | |
| tree | 304e1ab6dafc2bcaa87f1c5456f90cd6a7e06c82 /target-sh4 | |
| parent | target-sh4: Split out T from SR (diff) | |
| download | qemu-a2368e01c95a093d250a0e5d3cef53dddf642f1e.tar.gz qemu-a2368e01c95a093d250a0e5d3cef53dddf642f1e.tar.xz qemu-a2368e01c95a093d250a0e5d3cef53dddf642f1e.zip | |
target-sh4: optimize addc using add2
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/translate.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index bcdf4f39f9..5c90fe3f31 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -644,15 +644,12 @@ static void _decode_opc(DisasContext * ctx) case 0x300e: /* addc Rm,Rn */ { TCGv t0, t1; - t0 = tcg_temp_new(); + t0 = tcg_const_tl(0); t1 = tcg_temp_new(); - tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8)); - tcg_gen_add_i32(t1, cpu_sr_t, t0); - tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), t0); - tcg_gen_setcond_i32(TCG_COND_GTU, t0, t0, t1); - tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0); + tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); + tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, + REG(B11_8), t0, t1, cpu_sr_t); tcg_temp_free(t0); - tcg_gen_mov_i32(REG(B11_8), t1); tcg_temp_free(t1); } return; |