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| author | Aurelien Jarno | 2012-09-16 13:12:20 +0200 |
|---|---|---|
| committer | Aurelien Jarno | 2012-09-21 19:53:16 +0200 |
| commit | ed22e6f30e7f8c723f9b1be30869b9c0368e3e4e (patch) | |
| tree | e66412137c13c034c5bfa5a154ccf611e68e1406 /target-sh4 | |
| parent | target-sh4: optimize swap.w (diff) | |
| download | qemu-ed22e6f30e7f8c723f9b1be30869b9c0368e3e4e.tar.gz qemu-ed22e6f30e7f8c723f9b1be30869b9c0368e3e4e.tar.xz qemu-ed22e6f30e7f8c723f9b1be30869b9c0368e3e4e.zip | |
target-sh4: remove gen_clr_t() and gen_set_t()
gen_clr_t() and gen_set_t() have very few callers and can be remplaced
by a single line. Remove them.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/translate.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 9ecbe471e6..cdc4e3bc5f 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -339,16 +339,6 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) gen_jump(ctx); } -static inline void gen_set_t(void) -{ - tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); -} - -static inline void gen_clr_t(void) -{ - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); -} - static inline void gen_cmp(int cond, TCGv t0, TCGv t1) { TCGv t; @@ -519,7 +509,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); return; case 0x0008: /* clrt */ - gen_clr_t(); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); return; case 0x0038: /* ldtlb */ CHECK_PRIVILEGED @@ -537,7 +527,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); return; case 0x0018: /* sett */ - gen_set_t(); + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); return; case 0xfbfd: /* frchg */ tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); @@ -1660,7 +1650,7 @@ static void _decode_opc(DisasContext * ctx) */ if (ctx->features & SH_FEATURE_SH4A) { int label = gen_new_label(); - gen_clr_t(); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst); tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); |