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| author | blueswir1 | 2007-04-06 22:03:29 +0200 |
|---|---|---|
| committer | blueswir1 | 2007-04-06 22:03:29 +0200 |
| commit | 417454b0322ab1eed03615fe563d770fa7e4c9f9 (patch) | |
| tree | 7b5b41b662d32cfb64cc73b200f7a023c27c9c3a /target-sparc/translate.c | |
| parent | Enforce even float register pair for double register ops (Aurelien Jarno) (diff) | |
| download | qemu-417454b0322ab1eed03615fe563d770fa7e4c9f9.tar.gz qemu-417454b0322ab1eed03615fe563d770fa7e4c9f9.tar.xz qemu-417454b0322ab1eed03615fe563d770fa7e4c9f9.zip | |
Full implementation of IEEE exceptions (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2625 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 34a3357f97..0d71da3b86 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -943,6 +943,21 @@ static GenOpFunc * const gen_fcmpd[4] = { gen_op_fcmpd_fcc2, gen_op_fcmpd_fcc3, }; + +static GenOpFunc * const gen_fcmpes[4] = { + gen_op_fcmpes, + gen_op_fcmpes_fcc1, + gen_op_fcmpes_fcc2, + gen_op_fcmpes_fcc3, +}; + +static GenOpFunc * const gen_fcmped[4] = { + gen_op_fcmped, + gen_op_fcmped_fcc1, + gen_op_fcmped_fcc2, + gen_op_fcmped_fcc3, +}; + #endif static int gen_trap_ifnofpu(DisasContext * dc) @@ -1289,6 +1304,7 @@ static void disas_sparc_insn(DisasContext * dc) } else if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; + gen_op_clear_ieee_excp_and_FTT(); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); @@ -1476,6 +1492,7 @@ static void disas_sparc_insn(DisasContext * dc) #endif if (gen_trap_ifnofpu(dc)) goto jmp_insn; + gen_op_clear_ieee_excp_and_FTT(); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); @@ -1653,18 +1670,18 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 - gen_fcmps[rd & 3](); + gen_fcmpes[rd & 3](); #else - gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */ + gen_op_fcmpes(); #endif break; case 0x56: /* fcmped, V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 - gen_fcmpd[rd & 3](); + gen_fcmped[rd & 3](); #else - gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */ + gen_op_fcmped(); #endif break; case 0x57: /* fcmpeq */ |