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| author | blueswir1 | 2008-09-06 19:54:01 +0200 |
|---|---|---|
| committer | blueswir1 | 2008-09-06 19:54:01 +0200 |
| commit | 510aba20f0996e4c980d00a7cf90804685de20bf (patch) | |
| tree | eedda9d12d5b0c982f71b0b7749b3078c1ca680c /target-sparc | |
| parent | Convert most env fields to TCG registers (diff) | |
| download | qemu-510aba20f0996e4c980d00a7cf90804685de20bf.tar.gz qemu-510aba20f0996e4c980d00a7cf90804685de20bf.tar.xz qemu-510aba20f0996e4c980d00a7cf90804685de20bf.zip | |
Fix a typo in fpsub32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 4f134953c6..9dea1c4ea1 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3786,7 +3786,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fpadd32); + tcg_gen_helper_0_0(helper_fpsub32); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x057: /* VIS I fpsub32s */ |