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| author | Bastian Koppelmann | 2016-02-19 14:43:43 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2016-02-25 12:54:42 +0100 |
| commit | 518d7fd2a098730669c0a0707c031dcfe52ece9a (patch) | |
| tree | 08aa9ba407f551de623e81123c51c13e808e5d26 /target-tricore/cpu.h | |
| parent | target-tricore: Fix wrong precedences on psw_write (diff) | |
| download | qemu-518d7fd2a098730669c0a0707c031dcfe52ece9a.tar.gz qemu-518d7fd2a098730669c0a0707c031dcfe52ece9a.tar.xz qemu-518d7fd2a098730669c0a0707c031dcfe52ece9a.zip | |
target-tricore: Add trap handling & SOVF/OVF traps
Add the infrastructure needed to generate and handle traps and
implement the generation of SOVF and OVF traps.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1455889426-1923-2-git-send-email-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore/cpu.h')
| -rw-r--r-- | target-tricore/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h index be6f12170d..5fee376674 100644 --- a/target-tricore/cpu.h +++ b/target-tricore/cpu.h @@ -270,6 +270,7 @@ enum { TRAPC_ASSERT = 5, TRAPC_SYSCALL = 6, TRAPC_NMI = 7, + TRAPC_IRQ = 8 }; /* Class 0 TIN */ |